1. Field of the Invention
The present invention relates to a method for producing a semiconductor device, which is especially suitable to a method for producing a semiconductor device containing a bipolar transistor and a MOSFET of high-performance.
2. Description of the Related Art
Today, it is advancing to become electronic apparatuses smaller and lightweight with high-performance and multi-functions. By this reason, a bipolar-MOS hybrid LSI (hereinafter, referred to as a BiMOSLSI) is remarked which combining merits of high speed and high precision of a bipolar transistor and high integration and low power consumption of a MOSFET.
However, in the case of the conventional BiMOSLSI manufacturing process, there have been problems where the number of process steps increases as the respective performances of the bipolar transistor and the MOSFET become higher, and the cost of wafer process and TAT (turn around time) increase. Thus, uses of the products to which this producing method can be applied have been limited.
A conventional BiMOSLSI producing process is shown in FIGS. 1A to 1D, which show a sectional view of an upper portion of a silicon substrate of a bipolar transistor part and a P-channel MOS transistor part of double-polysilicon structure. The process flow is as follows.
(1-1) Process
At first, an N.sup.+ buried layer 1 and a diffusion layer 2 are formed in a bipolar-transistor part of a semiconductor substrate Sub. After production, the N.sup.+ buried layer 1 and the diffusion layer 2 function as a collector outlet of a NPN transistor.
Next, a LOCOS oxide film 3 and a P.sub.+ diffusion layer 4 for element isolation are formed, and then a gate oxide film 5 is formed. At this time, the LOCOS oxide film 3 is formed to have the thickness of 200 to 400 [nm], and the gate oxide film 5 is formed to have the thickness 10 to 20 [nm].
After that, a polysilicon film 6 having the thickness of about 100 to 200 [nm] is formed all over the surface by chemical vapor deposition (hereunder, referred to as CVD), and the polysilicon/gate-oxide laminated film of the base and emitter forming portion of the bipolar transistor part is then opened with the existing dry etching technique.
The polysilicon film 6 functions as a protective film for the gate oxide film 5. That is, it can be prevented that a deficiency of resisting pressure, etc. occurs due to a contamination of the gate oxide film in a resist exfoliation process at the time when the gate oxide film 5 is opened.
Further, the (1-2) process can prevent from a gate-oxide-film etching at the time of light etching by HF (hydrogen fluoride) before forming a second polysilicon film 7. The light etching remove a natural oxide film of an interface of the polysilicon-silicon substrate so as to decrease a contact resistance with the substrate. This is needed to utilize the polysilicon as an outlet electrode which is based on a contact with the substrate. The process of protecting a gate oxide film with a polysilicon is needed as the gate oxide film comes thinner to about 20 [nm] or less.
(1-2) Process
Next, the second polysilicon film 7 having the thickness of 100 to 200 [nm] is formed by CVD. Combination with the former polysilicon CVD makes the thickness of the polysilicon film amounts to 300 to 400 [nm].
Then, N.sup.+ ions are implanted into the gate-electrode portion of the MOS, and P.sup.+ ions are implanted into the base-electrode forming portion of the bipolar transistor part. After that, leaving the gate-electrode of the MOS and the base-electrode of the bipolar transistor part, the first and the second polysilicon films are processed by the existing dry etching technique. In this connection, N.sup.+ ions are implanted into the gate-electrode portion of the MOS in order to improve the characteristic of a N-channel MOS to be formed usually on the same substrate to have a surface-channel structure.
Next, P.sup.31 ions are implanted into the MOS part, and an LDD (lightly doped drain) diffusion layer 8 is formed. It is necessary to form the LDD diffusion layer 8 for the purpose of improving the hot-carrier resistance, as the gate length become more minute, that is, sub-micron to sub-half-micron.
Then, SiO.sub.2 having the thickness of 200 to 400 [nm] is formed by CVD, and an SiO.sub.2 spacer 9 for LDD is formed by anisotropic etching with the existing dry etching technique.
The region for forming the base and the emitter of the bipolar transistor is covered with polysilicon, so that it can be protected and not exposed to overetching at the time of forming the SiO.sub.2 spacer 9 for LDD by the anisotropic etching. Consequently, such problems as degradation of elements and deterioration of yield due to an RIE (reactive ion etching) damage do not occur. Then, P.sup.+ ions are implanted into the MOS part, and source and drain diffusion layers 10 are formed.
(1-3) Process
After an SiO.sub.2 film having the thickness of 300 to 400 [nm] is formed by CVD, an SiO.sub.2 /polysilicon laminated film of the region for forming the base and the emitter of the bipolar transistor is etched and removed by the use of existing dry etching technique.
Then, an SiO.sub.2 film having the thickness of 400 to 600 [nm] is formed by CVD, and an SiO.sub.2 spacer 11 for separating the emitter and the base electrode is formed by the anisotropic etching with the existing dry etching technique.
Next, a polysilicon 12 for forming an emitter is formed by CVD and then processed by the use of existing dry etching technique. Then, ions are implanted into the polysilicon 12 and diffused, so that a base and an emitter are formed.
The heat treatment of this time makes P.sup.+ diffusion from the base outlet electrode 7 so as to form a graft base, and, at the same time, the source and drain diffusion layer of the MOS part is activated.
(1-4) Process
The SiO.sub.2 film having the thickness of 300 to 400 [nm] is formed by CVD, and then respective electrodes are formed by the use of the existing wiring technique (not shown).
As is evident from a series of above procedures, there is a problem that added process steps are increased in accordance with forming of MOSFET and its elaboration and sophistication. To put it concretely, it is needed to perform CVD on a polysilicon film as a protecting film for a gate oxide film, and also it is needed to implant N.sup.+ ions into a gate-electrode portion of MOS.
Besides, it is needed to form the LDD diffusion layer and a source/drain diffusion layer. This causes increase of the number of process steps, and such a possibility as increasing of the processing cost and the TAT has been not avoidable.